Evaluation of the static performance of a simulation-stimulation interface for power hardware in the Loop
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This paper gives an evaluation framework of the static performance of a Simulation-Stimulation Interface (SSI) for Power Hardware in the Loop (PHIL) applications. The PHIL system is a hybrid system consisting of Hardware-Under-Test (HUT) connected to a Virtual Rest of the Power System (VROPS) via a Simulation-Stimulation Interface (SSI). The SSI maps the discrete time input/output signals of the VROPS to the continuous time power input/output signals of the HUT. Ideally, the performance of the PHIL should be the same as the actual power system consisting of the HUT connected to the Rest of the System hardware. The evaluation of the PHIL performance is made in terms of its electric power matching capability. Since the SSI is the key component affecting the power matching, this paper evaluates the effect of the SSI parameters on the static performance of PHIL, specifically, the power system loadability/maximum power transfer. The results are illustrated using P-Q curves of simple 2-bus l? system consisting of a generator, line and RL load. An experimental system was used to generate the baseline data for the simulation that was performed using Simulink. The study concentrated on the effect of time delay encountered in the SSI and VROPS processing on the maximum power transfer (i.e., P-Q curves) of the PHIL relative to that of the experimental system. The results show the decrease in maximum power transfer capability as the time delay increases to 1 msec. © 2003 IEEE.